1. Field of the Invention
The invention relates to phase-lock loop circuits, and more particularly to phase-lock loop circuits having improved acquisition time and stability with respect to varying input signal strengths.
2. Description of the Prior Art
Phase-lock loop circuits are widely used for demodulating amplitude modulated, frequency modulated and phase modulated signals. As shown in FIG. 1, these circuits generally comprise basic components, a phase detector, a loop filter, and a voltage controlled oscillator.
A signal to be detected is coupled to the phase detector and compared against the phase of the voltage controlled oscillator (VCO). The error signal provided by the phase detector is filtered by the loop filter and applied as a frequency control voltage to the VCO. This control voltage is applied to the VCO in a manner to alter its phase in a direction that reduces the phase difference between the input signal and the VCO output.
Acquisition time of a second-order phase-lock loop can be prohibitively long when the initial frequency offset between the input signal and the VCO output signal is large compared to the loop natural frequency. In conventional phase-lock loops, loop gain decreases when large phase errors are encountered, an effect which is opposite to that desired. When large phase errors are encountered, a high loop gain is desired to quickly reduce the phase error. After the error is reduced, the gain should be lowered to dampen the loop settling transient.
An improved version of a phase-lock loop circuit is described in "New Phase-Lock Loop Circuit Providing Very Fast Acquisition Time," Bernard S. Glance, IEEE Trans MTT, Vol MTT-33, No. 9, Sept. 1985, p. 747 ff. For small phase error the loop gain is designed for optimum transient damping. For large phase error the gain is increased to reduce the loop acquisition time accordingly. As shown in FIG. 2, the circuit differs from the conventional loop by the addition of a diode network in series with an active filter 2 of a conventional second order loop. Diodes 3 and 4 are shunted by a resistance 5 whose value is much less than the effective resistance of the diode pair in the non-conducting state. Diodes 3 and 4 remain in the non-conducting state until a predetermined forward bias voltage is exceeded. When diodes 3 and 4 are in the non-conducting state a normal gain factor is provided by resistors 5 and 6. This results in a normal operating zone as shown in FIG. 3. When the magnitude of the error signal from the phase detector exceeds a predetermined level one of the diodes conducts, shunting the resistor 5 by the diode forward resistance and reducing the input resistance coupled to the operational amplifier and thereby increasing the amplifier gain.
The circuit of FIG. 2 is not optimum from a noise threshold viewpoint. The present invention improves the noise figure while reducing the number of required components and provides the same dynamic response as does the Glance circuit shown in FIG. 2.
A further deficiency of conventional phase-lock loop circuits occurs when such circuits are used for demodulating FM or PM signals. In these applications when the applied input signal is not adequately limited, a varying input signal strength adversely affects the phase-lock loop performance. The present invention accepts an inadequately limited input signal and provides optimum performance from the phase-lock loop by eliminating the affect of the input signal amplitude on the open loop DC gain.